1. Field of the Invention
The present invention relates to semiconductor chip packages, and in particular, to dielectric headers used for mounting microwave semiconductor chips.
2. Description of the Related Art
Conventional discreet semiconductor devices (e.g. transistors) are typically encapsulated in packages consisting of a frame, or header, and a cover, from which multiple electrical leads protrude for providing electrical access to the active terminals of the semiconductor chip therein. The chip is typically mounted directly on the frame or header, e.g. via conductive or nonconductive epoxy, eutectic bonding, etc. The active terminals of the chip (e.g. the base, emitter and collector for a bipolar junction transistor ("BJT"), or the gate, source and drain for a field-effect transistor ("FET")) are coupled to the electrical leads, typically via wire bonds.
If the bottom surface (e.g. substrate) of the chip serves as one of the active terminals of the device (e.g. the collector for a BJT), an electrically conductive frame or header can be used and the chip can be conductively mounted thereto, such as by eutectically bonding its bottom surface to the conductive header. An example of this is illustrated in FIG. 1, wherein a transistor chip 10 is conductively coupled to, or mounted on, conductive metalization 12 deposited upon a dielectric header 14. Typically, such conductive coupling or mounting is done by eutectically bonding the transistor chip 10 to the metalization 12. The metalization 12 extends to and around a portion of the periphery 16 to the bottom side of the header 14 (often referred to as "wraparound").
Additional areas of metalization 18, 20, 22 are disposed near the mounting area of the transistor chip 10 so as to allow connections to be made to the terminal pads of the transistor chip 10. These connections are typically made by way of wire bonds 24, 26, 28, which are well known in the art.
These additional areas of metalization 18, 20, 22 also extend around portions of the periphery 16 to the bottom surface of the header 14. This extension of the metalizations 12, 18, 20, 22 to the bottom surface of the header 14 provides conductive paths for conductive electrical lead: 30, 32, 34, 36, which are used for electrically coupling the packaged transistor device into a circuit (not shown).
Two problems are associated with this mounting, or packaging, technique of transistor chips. The first problem, and typically the more serious problem, is the parasitic electrical impedance introduced by this transistor mounting technique. The second problem relates to the thermal impedance introduced, i.e. impedance to heat transfer from the transistor chip 10 to the heat sinking afforded by the transistor package leads 30, 32, 34, 36 and the circuit board to which it is typically soldered (not shown).
With respect to the problem of the parasitic electrical impedance, the wire bond and header metalization coupling each transistor terminal to its respective electrical lead presents undesirable parasitic electrical impedance. For example, the wire bond 26 and header metalization 20 coupling the base terminal 38 of the transistor chip 10 to its electrical lead 34 has an electrical line length associated therewith, thereby introducing parasitic inductance, as well as finite amounts of parasitic capacitance and resistance. Even where a wire bond is not used, such as in the connection of the collector terminal of the transistor chip 10 which is typically the bottom surface thereof, the electrical line length associated with its header metalization 12 nonetheless introduces parasitic inductance, capacitance and resistance. This problem is particularly acute at radio frequencies ("RF"), e.g. microwave.
With respect to the problem of thermal impedance, the internal heat generated within the transistor chip 10 during operation must pass through the header metalization 12 or the dielectric header 14 to reach the electrical leads 30, 32, 34, 36 in order to be dissipated by the lead sinking afforded thereby, as well as the heat sinking afforded by the circuit board to which the transistor package is normally connected (not shown).
Therefore, it would be desirable to have a semiconductor chip mounting or packaging technique which minimizes the parasitic electrical and thermal impedances associated with current semiconductor chip headers.